The present invention generally relates to programmable logic devices with multiple sized memories, and more particularly to programmable logic devices having memories with multiple sizes where one of these memories is a distributed memory formed at least partially using logic element lookup tables.
Programmable memory devices (PLDs) typically have one standard size of embedded memory block. When a block of memory greater than the standard size is desired, these standard sized memory blocks are chained together. However, this can decrease the speed with which the memory can be accessed. When a block of memory less than the standard size is desired, a portion of the standard sized memory block is unused, resulting in an inefficient use of silicon area.
In some PLDs, instead of an embedded memory, look-up-tables may be used as distributed memory. In these PLDs, the logic elements of the PLD are used as memory rather than having distinct blocks of memory. One disadvantage to using logic elements as memory is that they can be slower than dedicated memory blocks. Additionally, the use of logic elements as memory reduces the logic capacity of the device.
Thus, what is needed are circuits, methods, and apparatus that provide PLDs and other types of integrated circuits having highly flexible memory capabilities.